Presently there are significant efforts toward improving interconnect methods. The purpose is to provide lower sheet resistance in order to reduce the Ron (on resistance) X Area product of power integrated circuits and to lower the RC time constant of high frequency, wide bandwidth, high pulse rate circuits. One direction has been the use of copper Damascene because of the lower sheet resistivity of copper. For power circuits there has not been much progress other than to thicken and widen the interconnects.
There is a great deal of work being done on the use of a damascene metal scheme, whereby copper is used to provide a low resistance metal interconnect or power bus on a semiconductor device. This approach is being used for high current, high power devices, as well as for high frequency devices to lower their interconnect sheet resistance. The damascene metal scheme has attributes which include the lowering of the resistance of the interconnects, but is solely an interconnect scheme and does not improve the performance of the individual devices. The damascene approach has several disadvantages that are described below.
Firstly, the damascene metal scheme is costly and utilizes copper in place of standard aluminum/silicon/cu interconnects. It is well known that copper is difficult to process. The damascene metal scheme requires specialized equipment for depositing, etching and maintaining the integrity of the interconnect. For example, corrosion easily occurs and requires special equipment and techniques to prevent corrosion which adds time and cost to the product (i.e., dry in, dry out etching is required). In addition this metal then needs to be thickened to lower the sheet resistance.
This is done by a plating process that is expensive. Chemical/mechanical polishing (CMP) is required and is difficult since copper is prone to pitting and other defects, and fills the polishing pad. This scheme also requires that devices related to the CMP polishing be flat, which becomes increasingly difficult as more layers are added. All of these steps require a manufacturer to add equipment that is quite expensive and to develop new techniques using this equipment.
Accordingly, what is needed is a system and method for providing a power buss and interconnect method that overcomes the above-identified problems. The approach and method should be cost effective, easy to implement with existing equipment and processes and provide some technical advantages to devices within the semiconductor as well as providing a low sheet resistance interconnect. The present invention addresses such a need and is referred to as the buried power buss approach.